Cadence Design Techniques has introduced its Neo neural processing unit (NPU) know-how and NeuroWeave software program improvement package (SDK), aiming to enhance efficiency and effectivity with on-device machine studying and synthetic intelligence (ML and AI) workloads on the edge.
“For twenty years and with greater than 60 billion processors shipped, industry-leading SoC [System-on-Chip] clients have relied on Cadence processor IP for his or her edge and on-device SoCs. Our Neo NPUs capitalize on this experience, delivering a leap ahead in AI processing and efficiency,” claims Cadence’s David Glasco.
Cadence is making ready to launch a high-performance but energy-efficient neural processor, Neo, for on-device machine studying on the edge. (📷: Cadence)
“In right this moment’s quickly evolving panorama,” Glasco continues, “it’s important that our clients are capable of design and ship AI options based mostly on their distinctive necessities and KPIs [Key Performance Indicators] with out concern about whether or not future neural networks are supported. Towards this finish, we have made important investments in our new AI {hardware} platform and software program toolchain to allow AI at each efficiency, energy and value level and to drive the speedy deployment of AI-enabled methods.”
The Neo NPU cores are designed for high-performance machine studying on the edge, scaling from 8 giga-operations per second (GOPS) to 80 tera-operations per second (TOPS) of compute in a single core — and from there to “tons of of TOPS” by built-in a number of cores right into a single design. The corporate claims the design is constructed to help environment friendly offloading of workloads from any host processor, from utility processors all the best way all the way down to microcontrollers and digital sign processors (DSPs), and provides help for FP16 floating-point and INT16, INT8, and INT4 integer precision.
Drawing a direct comparability to the corporate’s first-generation AI {hardware}, Cadence claims the brand new Neo NPUs can ship “as much as 20X greater efficiency” with between two- and fivefold enhancements in inferences per second per space (IPS/mm²) and between five- and tenfold enhancements in inferences per second per watt (IPS/W). Precise efficiency is configurable relying on necessities, with Cadence claiming the IP may be configured between 256 to 32 multiply-accumulate (MACs) per cycle to stability energy, efficiency, and space necessities.
The {hardware} IP is joined by a unified software program improvement package, NeuroWeave, which helps most mainstream machine studying frameworks. (📷: Cadence)
On the software program facet, Cadence is supporting the Neo IP with a software program improvement package dubbed NeuroWeave. This, the corporate guarantees, provides a “uniform, scalable, and configurable software program stack” throughout each its Tensilica and Neo core IP with help for a variety of machine studying frameworks together with TensorFlow, TensorFlow Lite, and TensorFlow Lite Micro, ONNX. PyTorch, Caffe2, MXNet, and JAX, in addition to the Android Neural Community Compiler.
Extra data on the Neo NPU IP is accessible on the Cadence web site; the corporate has mentioned it’s focusing on common availability in December this yr, with unnamed “lead clients” having already begun “early engagements.”