Embedded {hardware} specialist Renesas has introduced its first totally in-house processor core based mostly on the free and open RISC-V instruction set structure (ISA) — marking a transfer away from utilizing third-party core designs, together with these from business big Arm.
“The growing reputation of the RISC-V ISA throughout the semiconductor business is a boon for innovation. It supplies designers with unprecedented flexibility and can slowly however steadily problem and remodel the present panorama of embedded techniques,” Renesas’ Giancarlo Parodi says of the know-how behind the corporate’s newest microcontroller. “Up to now, Renesas has embraced RISC-V know-how introducing 32-bit ASSP units for voice-control and motor-control constructed on CPU cores developed by Andes Expertise Corp. The thrilling subsequent step is the provision of [our] first in-house engineered CPU core.”
Renesas is making the bounce into CPU IP design, asserting its first in-house RISC-V core design — hitting the market early 2024. (📷: Renesas)
Whereas Renesas is not sharing full product particulars on the components which is able to use its in-house core but, it has confirmed a number of technical particulars in regards to the core itself. A block diagram exhibits a single 32-bit RISC-V core with performance-boosting dynamic department predictor, a {hardware} multiplier/divider, a vectored interrupt controller, a stack monitor register, separate instruction and knowledge buses ,and compact JTAG (cJTAG)/JTAG debug capabilities. It has additionally promised a 3.27 CoreMark per megahertz (CoreMark/MHz) efficiency degree — although at an as-yet unknown clock pace.
“This CPU is appropriate for a lot of completely different utility contexts. It may be used as important CPU or to handle an on-chip subsystem and even to be embedded in a specialised ASSP [Application-Specific Standard Product] system,” Parodi claims. “Clearly it is vitally versatile. Second, the implementation could be very environment friendly by way of silicon space, which helps cut back working present and leakage present throughout standby time, in addition to the apparent impact of smaller price influence. Third, regardless of concentrating on small embedded techniques, it supplies a surprisingly excessive degree of computational throughput to satisfy the more and more demanding efficiency requirement of even deeply embedded functions.”
Renesas has already launched components with RISC-V cores, however completely utilizing third-party IP from Andes Expertise. (📷: Renesas)
The core makes use of the free and open RISC-V instruction set structure, together with a number of of its extensions: Parodi says the core implements the RV32I or RV32E ISA with multiplication (M), atomic entry (A), compressed directions (C), and bit-manipulation (B) extensions. “That is the fantastic thing about the RISC-V ISA idea,” Parodi claims, “constructed from the ground-up to permit the designer to decide on which components to incorporate within the processor, depending on their goal use case, and in consequence optimize the trade-off between the ensuing energy consumption, efficiency, and silicon footprint.”
Renesas says it’s sampling silicon with the brand new core to “choose prospects” now, with the primary business chips resulting from launch within the first quarter of subsequent 12 months. Extra data is on the market in Parodi’s weblog put up.