Raspberry Pi has launched a draft datasheet for the RP1 enter/output (I/O) controller, a serious new function of the upcoming Raspberry Pi 5 and, technically talking, the primary in-house silicon the corporate ever began designing.
“Raspberry Pi 5 is probably the most sophisticated, and costly, engineering program we’ve ever undertaken at Raspberry Pi, spanning over seven years, and costing on the order of $25 million,” claims Raspberry Pi’s Eben Upton of the soon-to-launch single-board pc. “It is also our first flagship product to utilize silicon designed in-house right here at Raspberry Pi, within the type of the RP1 I/O controller.”
That RP1, which regardless of launching significantly after the also-designed-in-house RP2040 microcontroller on the Raspberry Pi Pico vary was really the primary mission for Raspberry Pi’s in-house chip design workforce, was added to the Raspberry Pi 5 so as to offload “low-speed” peripherals from the primary system-on-chip (SoC) — primarily in order that the general-purpose enter/output (GPIO) header may stay working at a 3.3V logic degree and luxuriate in 5V tolerance even whereas the SoC drops to 1.8V logic.
The RP1 handles the GPIO header, the MIPI Digital camera Serial Interface and Show Serial Interface (CSI and DSI) ports, the USB 2.0 and three.0 ports, the gigabit Ethernet port, the analogue video output — now not out there on the three.5mm AV jack, excised to make room for the dual CSI/DSI ports, however nonetheless current on an unpopulated pin header — and different low-speed peripherals required to match the performance of a Raspberry Pi 4’s BCM2711 SoC.
That is solely a part of the story, although: the draft datasheet launched in the present day dives into among the different options of the RP1 chip, together with the presence of two Arm Cortex=M3 processor cores, an eight-channel direct reminiscence entry (DMA) controller, three built-in fractional-N phase-locked loops (PLLs), a four-channel 12-bit-resolution analog-to-digital converter (ADC), 64kB of shared static RAM (SRAM), and built-in timebase mills which can be utilized to tempo DMA occasions or debouncing GPIO.
The RP1 shares what Upton describes as “a specific amount of inner infrastructure” with the RP2040, together with a programmable enter/output (PIO) block — however the two are very distinct elements.
At this time’s documentation launch features a block diagram, however some performance is being stored beneath wraps for now. (📷: Raspberry Pi)
Even this, although, is not an entire description of the chip’s capabilities. “Not like our documentation round our microcontroller product RP2040, in the present day’s launch doesn’t inform you every thing concerning the RP1 silicon that you simply would possibly wish to know,” Upton admits.
“As a substitute, it is there that can assist you port an working system and make use of the options of Raspberry Pi 5. Whereas we’re taking a look at exposing extra of the options of RP1, each in software program and with additional documentation, that’s going to be one thing you would possibly see a bit of in a while.”
The draft RP1 datasheet is offered to obtain from Raspberry Pi now, as a PDF.